Recently, the rapid progression of the microelectronic technology demands the devices with high speed which operate at low voltages to lessen the power consumption, as well as reduce the cost per unit chip. Hence, the method to approach such purpose is generally by scaling the device dimension down. For example, for CMOS device, by scaling to 0.1 .mu.m which operates at 1 V range is known to have the speed enhancement of about 3.times. as compared with the performance of a 0.35 .mu.m device at 3.3 V. However, in short-channel MOSFETs, the stringent issues may suffer, such as hot carrier effects, punchthrough effects, parasitic resistance etc., and are required to be overcome.
A double-diffused drain (DDD) or a lightly doped drain (LDD) technology has been proposed to alleviated hot carrier effects. The DDD structure allows little freedom in reducing maximum lateral electric field E.sub.max in the channel since the n- length cannot be easily controlled. On the other hand, LDD structures especially low-dose LDD, circumvent disadvantages and are beneficial in reducing E.sub.max ; nevertheless, the low-dose LDD structure is known to have faster spacer-induced degradation rates than transistors with higher substrate current I.sup.sub. As is reported in the reference, "T. Y. Huang, et al., "A New LDD Transistor with Inverse-T gate Structure", IEEE Electron Device Lett., EDL-8, p. 151 (1987)", Huang proposed a new submicrometer LDD transistor which eliminates the forgoing spacer-induced degradation. However, Huang also pointed out that the device with an inverse-T gate structure has about 2.5 times the overlap (C.sub.ov)(i.e. the capacitance between source/drain and the gate) than that of conventional LDD. The reason is due to its device structure with an entire LDD region under the gate. In addition, another parasitic capacitance--the gate fringe capacitor (C.sub.FR), around the gate electrode of a MOSFET and the junction capacitance (C.sub.J) are difficult to reduce too. The lager values of the parasitic capacitance give longer RC delay time.
Hence, minimizing parasitic capacitance is a key issue for realizing high speed and low-power ULSI. The C.sub.ov and C.sub.J can be reduced by adjusting the sidewall thickness, and by self-aligned counter well doping, or by implanting a channel impurity locally around the gate electrode, as is stated in the paper, "M. Togo, et al., "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs", Symp. On VLSI Tech. Dig., p. 38 (1996)." Besides, Togo et al. also proposed that the transistor with gate-side air-gap structure (GAS) could be used to minimize the C.sub.FR. The GAS in which a 5-nm-wide air gap formed next to the gate is found to reduce the fringe capacitance by half. Hence the gate delay time is reduced by 4.8 psec at fan out =1 and 16 psec at fan out =3 in a 0.25 .mu.m CMOS, and the power consumption is lowered compared to a conventional structure. In addition, the GAS structure does not be found to degrade electrical characteristics or reliability, as is depicted in the paper.
The fabrication of GAS structure as proposed by Togo is shown in FIGS. 1 (a)-(d), and will restate as following: After gate etching, a 20 nm wide Si.sub.3 N.sub.4 sidewall is fabricated (FIG. 1 (a)). Next a 50 nm thickness SiO.sub.2 layer 50 is formed, and is etched back (FIG. 1 (b)), after that, the Si.sub.3 N.sub.4 sidewall 20 is removed by wet etching to form the air gap 25 (FIG. 1(c)), and 50 nm thick SiO.sub.2 layer 60 is deposited to form the air-gap cap and is etched back (FIG. 1 (d)).